Multi-level metallization is commonly used in the integrated circuit industry to interconnect various components of a circuit and a system. Metals or metal alloys, such as copper or copper alloys, are used in these structures due to their low resistivity. FIGS. 1(a)–1(c) show an example of the fabrication of two parallel metal lines or other conductive structures in an insulator layer (oxide) 50 grown on a substrate. In this example, copper (Cu) is used as the conductor.
First, a barrier layer 52 and a seed layer 54 are deposited over the whole structure as shown in FIG. 1(a). A layer 100 of Cu is then deposited as shown in FIG. 1(b), by a technique such as electroplating, over the seed layer. The barrier layer, which remains, is not shown in FIG. 1(b). An etching, electrochemical etching, or chemical mechanical polishing (CMP) process is then carried out to remove the copper from the field regions 58 and leave it in the channels or other types of features 56 formed in the insulator layer as shown in FIG. 1(c).
The process of FIGS. 1(a)–1(c) depicts an ideal situation. In practice, it is extremely difficult to obtain the structure of FIG. 1c. FIG. 2 shows the actual cross section of a structure that one may get. Defects, such as dishing 60 and copper remnants 62, can be observed in the channels or other features 56 and over the field regions 58, respectively. Dishing presents a problem because it produces a non-planar surface and increases the resistance of the line. Copper remnants can cause shorts between conductive lines. These defects can be caused by the CMP process (incomplete removal from the field regions and too much removal from the features or channels) as well as by the etching process or the electroetching process.
FIG. 3(a) is a view similar to FIG. 1(b) but is somewhat enlarged and shows the barrier layer 52, which is not shown in FIG. 1(b). FIG. 3(a) also shows only one channel or other type of feature 56 and two adjacent field regions 58. Feature or channel dimensions can vary widely, but in order to roughly illustrate the scale of the illustrations provided by FIGS. 3(a)–3(d), it will be assumed that the feature width W in FIG. 3(a) is 100 μm and the feature depth D is 6 μm. FIG. 3(a) also illustrates, schematically, the small-grained structure of the Cu layer 100 deposited over the barrier layer 52 on the insulator layer 50.
Conventionally, after the Cu layer 100 has been deposited on the barrier layer overlying the insulator layer 50 as shown in FIG. 3(a), the Cu layer is annealed so as to enlarge its grain structure. FIG. 3(b) illustrates, schematically, the relatively large-grained structure of the Cu layer 100 after annealing.
The etching, electrochemical etching, or CMP process carried out to remove Cu from the field regions 58 is conventionally performed after the annealing operation. FIG. 3(c) shows the structure of the copper layer 100 after the layer has been partially removed from over the field regions 58 by the etching, electroetching, or CMP process. FIG. 3(d) shows the insulator layer and barrier layer structure, with a copper conductive structure remaining in the line, i.e. the channel or other type of feature 56, after the copper layer has been completely removed from the field regions 58 by the selected process. FIG. 3(d) also shows dishing 60 in the copper conductive structure left in the channel or other feature 56 which results from the conventional copper deposition, annealing and copper removal process.